The present invention relates to an interface circuit located between signal lines that transfer signals, and, more specifically, to a semiconductor device such that an interface circuit disposed between buses formed on a semiconductor chip facilitates smooth transfer of information among module circuits.
With rapid advances in miniaturization technology for forming high-density semiconductor circuits on a semiconductor substrate, it has been possible to implement semiconductor integrated circuitry with high levels of functionality on a single semiconductor chip. Functions of the integrated circuitry are classified according to their purpose into, for example, a central processing circuit, a memory circuit, an input/output circuit, and so forth. These functions are subdivided into further details and implemented as module circuits. Users and manufacturers of integrated circuits select from those module circuits functions to achieve their purpose and implement on a semiconductor substrate a single integrated circuit for achieving their desired functionality.
These module circuits are required to exchange information with each other in order to realize their functionality and are connected to signal lines, or so-called buses, for transmitting such information to and from each other. The buses are classified into address buses, data buses, control buses, and so forth according to the information transmitted.
Resistance and stray capacitance of the signal line itself delay the signal propagating over the bus. Increases in operating frequency, along with increased density of integrated circuitry, have led to a situation where the wiring distance of the bus is restricted. Delays in signal propagation and degradation in signal waveforms make it difficult to maintain the overall operation of the integrated circuitry as appropriate, thus resulting in malfunction. In order to address such a problem, an interface circuit is provided on the bus to send and receive signals; the above problem is prevented by shortening the transmission length of the bus. For example, as disclosed in Japanese Patent Laid-Open No. 8-123591 (Multiplexed Bus Circuit), a circuit portion is disposed on a bus to shorten the transmission length of the bus, thereby preventing degradation in signal waveforms and decreases in time margin.
However, the afore-mentioned circuit portion employs such an arrangement that address, data and control information propagating over the bus is temporarily stored in a latch circuit and sent over the bus after a predetermined number of clock cycles. Especially, address and data information is bidirectionally latched, so that it is sent over the bus after a predetermined number of clock cycles. With such an arrangement, for example, when the data stored in the memory is to be fetched, at least two delays are introduced in said circuit portion until desired data is fetched by the central processing unit after a fetch instruction of the central processing unit is sent, thereby unnecessarily reducing the overall processing speed of the integrated circuitry.
The present invention is intended to overcome the above problem and provides an interface wherein for information sent from a central processing unit, no time delay is introduced in an interface circuit, while for information sent from a extended bus to the central processing unit, a predetermined time delay is introduced in the interface circuit, thereby ensuring a transmission length of the overall bus and alleviating reductions in overall processing speed of the integrated circuitry.